In general, the circuit board is formed by laminating a plurality of patterned circuit layers and dielectric layers in alternation. The patterned circuit layers are fabricated by patterning the copper foils through the lithography and etching processes. The dielectric layers are disposed between the patterned circuit layers to isolate the patterned circuit layers. The stacked patterned circuit layers are electrically connected through the plating through holes or conductive vias penetrating the dielectric layer(s). Then, the chip is disposed on the surface of the circuit board and electrically connected through the internal circuit for signal transmission. However, along with the market demands, the design of the chip package structure move toward lightness, compactness and portability, and the surface area of the circuit board available for chip mounting is very limited.
Because the chip is generally soldered to the circuit board of the package structure and the electro-magnetic interference (EMI) exists, a faraday cage is commonly placed to shield the EMI. The principle of the faraday cage is to apply a conductive shield (such as, a metal cover) to reflect the electrical interference or transfer the electrical interference to the ground. Nevertheless, the faraday cage surrounding the chip also increase the size and weight of the chip package structure, which is adverse to minimization of the chip package structure.